1. Technical Field
The present invention relates, generally, to a method of manufacturing a metal oxide semiconductor (MOS) transistor. More particularly, the present invention relates to a method of manufacturing a complementary metal oxide semiconductor (CMOS) transistor having a lightly doped drain (LDD) structure in a semiconductor device.
2. Description of the Related Art
As technologies for manufacturing semiconductor devices have been developed and applications for memory devices have been expanded, memory devices having increased capacities have been required. In particular, integration density of a DRAM device, which includes memory cells composed of one capacitor and one transistor, has been remarkably improved.
A MOS transistor is widely employed in the DRAM device. A conventional MOS transistor having an LDD structure is disclosed in U.S. Pat. No. 5,956,591 and Japanese Laid Open Patent Publication No. 2000-311951.
FIG. 1 is a cross-sectional view illustrating a conventional MOS transistor, and FIG. 2 is an enlarged cross-sectional view of portion ‘A’ in FIG. 1. Referring to FIG. 1, a MOS transistor includes a gate insulation layer pattern 12 and a gate 14 formed on a semiconductor substrate 10 including source/drain regions 16. The source/drain regions 16 have an LDD region 16a and a highly doped drain (HDD) region 16b contacting the LDD region 16a. The LDD region 16a having a low impurity concentration is formed in a portion of the substrate 10 adjacent to the gate 14 while the HDD region 16b having a high impurity concentration is horizontally extended from the HDD region 16a. 
The MOS transistors are generally divided into an N type MOS transistor and a P type MOS transistor in accordance with a type of a channel thereof. When the P type MOS transistor and the N type MOS transistor are formed on a semiconductor substrate, the combination of the P type and the N type MOS transistors form a CMOS transistor.
As the semiconductor devices become more highly integrated, a length of a gate of a MOS transistor decreases such that the MOS transistor has a very short channel having a length of less than a micrometer. Thus, several problems may occur in the MOS transistor because the MOS transistor has an extremely short channel, e.g., a short channel effect or punch-through. As a result, electrical characteristics of the MOS transistor deteriorate.
In particular, when the MOS transistor has the above-mentioned LDD structure, the LDD region 16a may be extended beneath the gate insulation layer pattern 12 so that the LDD region 16a may be overlapped with the gate 14 by a predetermined overlap length D, as shown in FIG. 2. When the overlapped length D is disadvantageously long, the channel length of the MOS transistor is reduced and a parasitic capacitance is increased due to the overlap between the LDD region 16a and the gate 14. On the other hand, when the overlapped length D is extremely short, the mobility of dopants may be reduced in the channel region of the MOS transistor, thereby decreasing an operation speed of the MOS transistor. Hence, the overlapped length D between the LDD region 16a and the gate 14 should be optimized to obtain a MOS transistor having desired electrical characteristics.
The overlap between the LDD region and the gate generally occurs in accordance with a horizontal diffusion of impurities implanted into the LDD region. To prevent the overlapped length from being extremely elongated according to an excessive diffusion of the impurities, the impurities may be implanted into the LDD region using a gate having a spacer as a mask after forming the spacer on a sidewall of the gate. Here, since the impurities implanted into the LDD region are spaced apart from the gate by a thickness of a spacer, the excessive elongation of the overlapped length may be prevented although the impurities are diffused toward the gate during subsequent manufacturing processes.
To form a CMOS transistor, however, when an N type MOS transistor and a P type MOS transistor have LDD regions, respectively, N type impurities may have a different diffusion length than a diffusion length of P type impurities. Generally, the N type impurities have a diffusion length shorter than that of the P type impurities. Thus, although spacers are formed on sidewalls of gates of the N type and P type MOS transistors to adjust overlapped lengths between the gates and the LDD regions, the overlap length of the N type MOS transistor may be different from that of the P type MOS transistor.
To prevent an increase of the overlap length as discussed above, a method of forming a CMOS transistor is disclosed in U.S. Pat. No. 6,316,302. In the method of forming a CMOS transistor, N type impurities are implanted into an N type transistor area of a substrate to form an N type LDD region using a gate pattern as a mask. After forming a spacer on a sidewall of the gate pattern, P type impurities are implanted into a P type transistor area of the substrate using the gate pattern including the spacer as a mask, thereby forming a P type LDD region. Since the P type LDD region is formed spaced apart from the gate pattern by a thickness of the spacer, an excessive increase in an overlap length between the P type LDD region and the gate pattern may be prevented. However, because an additional etching process is performed on the substrate including the N type LDD region to form the spacer on the sidewall of the gate pattern, a surface of the N type LDD region may be damaged during the etching process. When the N type LDD region is damaged, a surface resistance of the N type LDD region may be significantly increased, thereby deteriorating electrical characteristics of the CMOS transistor.